FIG. 8 shows a typical active-matrix-type image display device in prior art, and gives illustration as a block diagram showing an electric structure of a liquid crystal display device 1. The liquid crystal display device 1 schematically includes: a display section 2; a scanning signal line driving circuit gd; a data signal line driving circuit sd; and a control signal generating circuit ctl. In the display section 2, as described above, there is provided a pixel PIX at each area sectored by a plurality of scanning signal lines g1, g2, . . . , gm (hereinbelow shown by a reference sign g when they are collectively referred) and data signal lines s1, s2, . . . , sn (hereinbelow shown by a reference sign s when they are collectively referred).
As shown in FIG. 9, the pixel PIX includes: an active element SW and a pixel capacitor Cp. When the scanning signal line g is selected, the active element SW leads an image signal DAT of the data signal line s to the pixel capacitor Cp, so as to maintain the display state while holding the image signal DAT also during the non-scanning period. The pixel capacitor Cp is constituted of a liquid crystal capacitor CL and an auxiliary capacitor Cs.
The data signal driving circuit sd is constituted of a shift resistor 3 and a sampling circuit 4. In the data signal driving circuit sd, the shift resistor 3 performs sampling with respect to the image signal DAT that has been inputted to an analog switch of the sampling circuit 4 in synchronism with timing signals such as (a) a clock signal CKS from the control signal generating circuit ctl, (b) an inversion signal CKSB corresponding to CKS, and (c) a data scanning start signal SPS, so as to write the image signal DAT that has been subjected to the sampling in the respective data signal lines s as required.
The scanning signal line driving circuit gd is constituted of a shift resistor 5, and selects the scanning signal line g sequentially in synchronism with the timing signals such as (a) a clock signal CKG from the control signal generating circuit ctl and (b) a scanning start signal SPG, so as to control ON/OFF of the active element SW disposed in the pixel PIX. When the active element SW is ON, the image signal DAT in the data signal line s is written in the pixel PIX so as to be held by the pixel capacitor Cp disposed in the pixel PIX as described above. The operation described above is repeatedly performed, so that it is possible to display images on the display section 2.
FIG. 10 is a wave form chart showing an example of a drive wave form of the foregoing writing operation. In this example, a horizontal-line-inversion-type driving method is employed. The image signal DAT is outputted from the control signal generating circuit ctl and is inputted to the data signal line driving circuit sd, in synchronism with the clock signals CKS, CKSB, and the data scanning start signal SPS. In response to the clock signals CKS, CKSB, and the data scanning start signal SPS, selective pulses are sequentially outputted to odd-numbered scanning signal lines (g1, g3, . . . ) and even-numbered scanning signal lines (g2, g4, . . . ), and the image signals DAT are sequentially written in the pixels of the respective data signal lines s1 (s1, s2, . . . ). In this example, image signals of positive polarity are written in the pixels of the odd-numbered scanning signal lines (g1, g3, . . . ), and image signals of negative polarity are written in the pixels of the even-numbered scanning lines (g2, g4, . . . ).
Incidentally, realization of low power consumption in an image display device is more and more desired recently. As one measures for satisfying the desire, there is provided a low-frame-frequency driving method in which a non-scanning period is set to be sufficiently longer than a scanning period so as to realize low power consumption in a case where a static image or a time-varying image of a low refresh rate is displayed while a standby image is being displayed. In the low frame frequency driving method, an image is written in the pixel PIX at one frame as described above, and scanning is stopped for several (2 to 8) frames, so that the non-scanning period is set to be sufficiently longer than the scanning period. FIG. 11 shows how the data signal line driving circuit sd is operated in accordance with the low-frame-frequency driving method.
During the scanning period, the selective pulses are sequentially derived to the scanning signal lines g1, g2, . . . . Corresponding to this, the image signal DAT whose polarity is inverted at each horizontal scanning period in accordance with the horizontal-line-inversion-type driving method is inputted from the control signal generating circuit ctl, and a level corresponding to an i-numbered data signal line si is outputted to an arbitrary data signal line si by the sampling circuit 4. A level of the data signal line si at a timing when the selective pulse drops is written in the respective pixels PIX1, PIX2, . . . , so as to be held over the non-scanning period at more than one frame period described above.
Here, as shown in FIG. 12, as to the pixels PIX1 and PIX2 corresponding to the arbitrary data signal line si and the scanning signal lines g1 and g2, the following operation is performed: in a case where the low frame frequency drive is performed, electric charges held in the pixel capacitors Cp of the pixels PIX1 and PIX2 during the scanning period are separated from the data signal line si by the active element SW after the scanning period. However, a voltage VDS is actually applied to a line between a source and a drain of the active element SW. Further, capacitance of the data signal line si is much larger than that of the pixel capacitor Cp.
Thus, if the data signal line si is left at a potential in finishing the scanning after the scanning period, there occurs such problem that: as the source/drain voltage VDS, that is, a difference between a potential of the pixel capacitor Cp and a potential of the data signal line si is larger, a leak current occurs, so that the electric charge held in the pixel capacitor Cp may leak. In order to solve the problem, a method for minimizing influence exerted on the display state by the leak current is employed, for example, the auxiliary capacitance is made larger.
However, the leak current varies according to the source/drain voltage VDS as described above, and it is typical that different charges (potentials) are held in the respective pixels PIX according to display images, so that the source/drain voltage VDS varies for the respective pixels PIX. In this manner, the leak current varies for the respective pixels PIX, so that the display quality may be deteriorated.
Particularly in a liquid crystal display, ac drive is required. Thus, in the horizontal line inversion drive type for example, electric charges different in polarity such as positive and negative are held in upper and lower pixels adjacent to each other. Thus, as shown in FIG. 13, in a case where, for example, a charging potential of the data signal line si is negative when the scanning period comes to an end so as to shift to the non-scanning period, the source/drain voltage VDS2 is small in the pixel PIX2 holding a negative charge. On the other hand, the source/drain voltage VDS1 is large in the pixel PIX1 holding a positive charge, and a leak current is larger, so that there occurs such problem that: display concentration of the pixel having the positive charge in the non-scanning period fades away (in a case of normally white).